A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC
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چکیده
A 12b 2MS/s cyclic ADC achieves low power consumption with a single-ended rail-to-rail input signal range of 3.3Vp-p. The proposed voltage reference scheme directly employing power supply voltages implements an offset voltage less than 1mV without well-known calibration and trimming techniques. The prototype ADC in a 0.18mm CMOS technology demonstrates the effective number of bits of 11.48 for a 100kHz full-scale input at 2MS/s. The ADC with an active die area of 0.12mm2 consumes 3.6mW at 2MS/s and 3.3V(analog)/1.8V (digital).
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تاریخ انتشار 2008